Structure for nano-scale metallization and method for fabricating same

ABSTRACT

A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. application Ser.No. 12/885,665, filed on Sep. 20, 2010, the contents of which areincorporated by reference in their entirety herein.

FIELD OF THE INVENTION

The present invention relates to a semiconductor structure, and a methodof fabricating the same. More particularly, the present inventionrelates to nano-scale semiconductor metallization that can have higherthan conventional aspect ratios and is compatible with very low kdielectric materials. The present invention also provides a method tofabricate such structure while substantially reducing failure due tomisalignment, flawed metal deposition, and electromigration.

BACKGROUND OF THE INVENTION

Generally, integrated circuits include a complex network of conductiveinterconnects fabricated on a semiconductor substrate in whichsemiconductor devices have been formed. Efficient routing of theseinterconnects requires formation of multilevel or multilayered schemes,such as, for example, single or dual damascene wiring structures.

Within an interconnect structure, conductive vias run perpendicular tothe semiconductor substrate and conductive lines run parallel to thesemiconductor substrate. According to conventional damascene processing,lines and vias are created within a dielectric layer. A dielectric layeris patterned to create grooves which become lines and holes which becomevias. Metal is deposited on the patterned surface such as byelectroplating to fill the grooves and holes. Excess is removed, such asby CMP, thereby forming lines along the top of a given dielectric layer,and forming vias which extend below the lines in order to connect to anunderlying layer.

Copper or a Cu alloy has recently been preferred to form the conductiveinterconnects to provide high speed signal transmission betweentransistors on a complex semiconductor chip. Copper typically requires abarrier layer to prevent it from migrating into, and thereby degradingthe insulating capacity of, surrounding dielectric material. As featuresizes continue to decrease in the ongoing development of more and moredensely built integrated circuits, the limitations of dielectricdamascene and copper are increasingly apparent. For one, smaller featuresize of the conductive features generally requires higher aspect ratio,and it is increasingly difficult to fill such features to form void freemetal structures. Forming a barrier layer within high aspect features isparticularly difficult. Furthermore, as feature sizes continue todecrease, the barrier cannot scale and hence constitutes a greaterfraction of any particular feature. Additionally, as the featuredimensions become comparable to the bulk mean free path, the effectiveresistivity of copper features will increase because of nonnegligibleelectron scattering at the copper-barrier interface and at grainboundaries. See Pawan Kapur et al., Technology and ReliabilityConstrained Future Copper Interconnects—Part 1 Resistance Modeling, 49:4, IEEE Transactions on Electron Devices 590 (Apr. 2002).

Some challenges associated with copper damascene can be avoided byforming the interconnect structure by an alternate metal usingsubtractive metal etch (“SME”), as for example is discussed in U.S. Pat.No. 5,512,514 (“Saile”). In SME, a metal layer is deposited, then etchedaccording to one or more patterns to remove all but the interconnectstructures. For example, referring to FIG. 1 which represents a priorart integrated circuit according to Saile, an isolation layer 12overlies a semiconductor substrate 10. A first metal stack is formed bydepositing a first metal layer 21, an optional etch stop layer 22; asecond metal layer 23, and an anti-reflective coating layer 24. Thestack is etched through to isolation layer 12 according to a first maskfor first conductive lines, which mask is formed over layer 24 bypatterning a first photoresist layer. The stack is then etched throughto etch stop layer 22 according to a second mask for first vias, whichmask is formed by patterning a second photoresist layer. A dielectriclayer 25 is deposited over the exposed substrate and the etched featuresto fill the voids formed by such etch steps. A second interconnect layerof lines 31, vias 33, and dielectric 35 can be formed by repeating theprocess. According to this SME process, that portion of such a nth metalstack covered by both n-level masks forms the vias, and results withinthe nth dielectric layer, self-aligned vias that extend above metallines.

A problem with forming multi-layered interconnect structure bysubtractive metal etch, however, is the difficulty of correctlypositioning features in an upper layer such that they align withfeatures in an underlying layer. Alignment is difficult because theunderlying features are not visible under the opaque upper metal layer.

SUMMARY OF THE INVENTION

According to the present invention, the problem of enabling theformation of structures by subtractive etch in proper alignment withfeatures underlying an opaque layer is solved by establishing a firstsurface topography that maps to the features of interest, forming anopaque layer over the first surface whereby such topography is retained,and referencing that topography to form structures aligned with suchunderlying features. The invention enables formation of a semiconductorinterconnect structure that can have higher than conventional aspectratios, and provides a method to fabricate such structure whilesubstantially reducing failure due to misalignment and electromigrationrelative to existing semiconductor interconnect structures.

In one embodiment, the invention provides a method that includes formingan opaque layer over a first layer, the first layer having a surfacetopography that maps to at least one feature therein, wherein the opaquelayer is formed such that the surface topography is visible over theopaque layer. A second feature is positioned and formed in the opaquelayer by reference to such surface topography.

In another embodiment, the invention provides a method to form metalinterconnects on substrate having a top layer that includes at least oneconductive element within dielectric material. The method includesselectively removing a portion of the dielectric material to define atleast one topographic feature and a surface topography on the surface ofsaid top layer; and forming a metal layer having substantially the samesurface topography over that top layer.

In addition to providing the above described methods, the presentinvention also provides an interconnect structure. The interconnectstructure has at least two layers on a substrate, such layers includingmetal interconnect structure embedded within dielectric material. Eachof such layers includes at least one via that extends to the top of thatlayer and at least one line formed along the bottom of said layer, andat least one via of the lower layer extends into the upper layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross section of a prior art interconnect structure.

FIGS. 2A-2F illustrate a first exemplary structure according to anembodiment of the present disclosure.

FIGS. 3A and 3B are respectively plan views of exemplary via and linemasks for an embodiment of the present disclosure.

FIGS. 4A-4C illustrate vertical cross-sectional views of a secondexemplary structure according to an embodiment of the presentdisclosure.

FIGS. 5A and 5B are respectively plan views of exemplary via and linemasks for an embodiment of the present disclosure.

FIG. 6 is a cross sectional view of another embodiment of the presentdisclosure.

FIG. 7 is a cross sectional view of another embodiment of the presentdisclosure.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will now be described in greaterdetail by reference to the drawings that accompany the presentapplication. It is noted that the drawings of the present applicationare provided for illustrative purposes only and are not drawn to scale.

In the following description, numerous specific details are set forth,such as particular structures, components, materials, dimensions,processing steps and techniques, in order to provide a thoroughunderstanding of the present invention. However, it will be appreciatedby one of ordinary skill in the art that the invention may be practicedwithout these specific details. In other instances, well-knownstructures or processing steps have not been described in detail inorder to avoid obscuring the invention.

It will be understood that when an element as a layer, region orsubstrate is referred to as being “on” or “over” another element, it canbe directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

Referring now to FIG. 2A, a first exemplary structure according to afirst embodiment of the present disclosure includes a substrate 201, anda first metal layer 220. Intermediate layer 210 is optional and may bean etch stop layer. First metal layer 220 may be deposited by any knowndeposition process and is preferably a conformal layer withsubstantially uniform thickness d1. FIG. 2A illustrates a mask layercomprising an organic planarizing layer 242 covered by an optional hardmask 244. First photoresist layer 245 can be patterned by exposing thephotoresist to radiation according to a pattern such as that depicted byFIG. 3A and developing the exposed photoresist utilizing a conventionalresist developer.

The substrate 201 may comprise a semiconducting material, an insulatingmaterial, a conductive material or any combination thereof. When thesubstrate is comprised of a semiconducting material, any semiconductorsuch as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InP and other III/Vor II/VI compound semiconductors may be used. In addition to theselisted types of semiconducting materials, the present invention alsocontemplates cases in which the semiconductor substrate is a layeredsemiconductor such as, for example, Si/SiGe, Si/SiC,silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs).Further, the substrate 201 can be single crystalline, polycrystalline,amorphous, or have a combination of at least two of a single crystallineportion, a polycrystalline portion, and an amorphous portion.

When the substrate is an insulating material, the insulating materialcan be an organic insulator, an inorganic insulator or a combinationthereof including multilayers. When the substrate is a conductingmaterial, the substrate may include, for example, polySi, an elementalmetal, alloys of elemental metals, a metal silicide, a metal nitride orcombinations thereof including multilayers. When the substrate comprisesa semiconducting material, one or more semiconductor devices such as,for example, complementary metal oxide semiconductor (CMOS) devices canbe fabricated thereon. When the substrate comprises a combination of aninsulating material and a conductive material, the substrate mayrepresent a first interconnect level of a multilayered interconnectstructure.

First metal layer 220 is conductive and can be any metal that can be dryetched (such as Al) including but not limited to Al, Cr, Hf, Ir, Mo, Nb,Os, Re, Rh, Ru, Ta, Ti, W, V, Zr, and alloys thereof. First metal layer220 is preferably formed by one or more of Aluminum, Ruthenium,Tungsten, Tantalum, Titanium or Tungsten. First metal layer 220 cancomprise two or more separately deposited materials, which can bedeposited in layers, or may form separate regions of said layer.According to one embodiment, a thin under layer can be formed to promotea characteristic in a subsequently formed main metal layer, for example,a particular crystal form or a specific crystal orientation. Thematerial of such under layer would depend upon the material of the mainmetal layer. Alternatively, an under layer could constitute an etchstop. In another embodiment, an earlier-formed layer may ultimatelyconstitute a conductive line while a later-formed layer may ultimatelyconstitute a via extending up to the next layer from such conductiveline. In yet another embodiment, a first metal can be formed withinfirst open regions of a patterned layer, then second openings can beformed in such patterned layer, and a second metal region can be formedby filling such second openings.

Returning to FIG. 2A, mask layer 242 can be an organic planarizing layer(‘OPL’) which can be formed of polyimide class materials or commerciallyavailable ODL, e.g., JSR NFC series or Shin Etsu ODL series. Mask layer244 can be a hard mask formed of, for example, silicon oxide, SiN, orsilicon-containing antireflective material (SiARC). Mask layers 242 (and244) can be patterned by dry etching (such as, for example, reactive ionetching, ion beam etching, plasma etching or laser ablation), and/or awet chemical etching process. FIG. 2B shows that selectively etchingmetal layer 220 to a depth d2 can transfer the pattern of mask 242 intothe upper portion of first metal layer 220 whereby is formed protrusions221 and 222 having height d2. Such selective etch can be by plasmaetching, and when layer 220 comprises tungsten, can be a fluorine basedplasma etch.

According to one embodiment, mask 242 is patterned to block subtractiveetch only of those portions of metal layer 220 that will become vias. Inanother embodiment, mask 242 could be first patterned to mask thatportion of metal layer 220 that will become lines. According to a thirdembodiment, a pattern such as that of FIG. 3A can be used to form mask242 that protects from etching portions of metal layer 220 in additionto those portions that will be vias.

A second patterning sequence can complete the patterning of metal layer220. As shown in FIG. 2C, a second mask layer including organicplanarizing layer 252 covered by optional hard mask 254 can be depositedover exposed metal layer 220. The same materials that are suitable forlayer 242 are suitable for layer 252, and layer 252 need not be the samematerial as layer 242. The same materials that are suitable for layer244 are suitable for layer 254, and layer 254 need not be the samematerial as layer 244. First mask 242 (and 244) can optionally beremoved prior to deposition of layer 252 (and 254) such as by ashing. Ifmask layers 252 and 254 are not sufficiently flat, they can beplanarized by known methods. Photoresist layer 255 can be deposited andpatterned by know methods, as can photoresist layer 245.

According to some embodiments, the first mask pattern, such as that ofFIG. 3A, results in relatively few protrusions such as 221 and 222corresponding to mask elements 301 and 302. If such protrusions aresufficiently spaced and appropriately shaped, then spin-on deposition oflayers 252 and 254 can fill between such protrusions and can form layersof substantially uniform depth without additional planarization steps.Optionally, layers 252 and 254 can have the same depths as layers 242and 244 respectively. Second photoresist layer 255 can be patternedaccording to a second pattern, such as that of FIG. 3B, which mask wouldretain structures corresponding to mask elements 303, 304, 305, 306, and307.

After patterning mask layer 252 (and 254, if present,) according to thepattern of photoresist layer 255, the pattern can be etched throughfirst metal layer 220 as depicted in FIG. 2D. This second etch could betimed or otherwise controlled, such as by inclusion of etch stop layer210, to end after etching depth d3. Those portions of metal layer 220masked by both the first and second masks (e.g., regions 310 in FIG. 3B)remain as vias which extend above those portions of metal layer 220masked by just one or the other of said masks. The etch depth d2 couldbe equal or different from etch depth d3. An embodiment using patternsexemplified by FIGS. 3A and 3B would form structure 215 comprising a viaof height d1 in perfect alignment with a line patterned by masks 302 and305. The structure formed by 302 where it does not overlap 305 wouldhave a thickness d1-d3, whereas that structure formed by 305 where itdoes not overlap 302 would have a thickness d1-d2. Similarly, thoseportions masked by 303, 306, and 307 (which have no overlap with masks301 and 302) would have a thickness of d1-d2.

While the foregoing contemplates just two patterning masks per metallayer, the present invention can utilize more than two masks to patternmetal layer 220, in which case those portions covered by all such maskswould remain as vias, and those portions covered by at least one, butfewer than all such masks would remain as lines. Those lines may, butneed not, all become functional conductive interconnects.

Referring now to FIG. 2E-1, after the patterning of metal layer 220 iscomplete, dielectric material 260 can be deposited to fill the voidsformed by the foregoing patterning steps. Dielectric material 260 can beany interlevel or intralevel dielectric (ILD), including inorganicdielectrics or organic dielectrics, and can be porous or non-porous.Examples of suitable dielectrics that can be used as dielectric material260 include, but are not limited to SiN, SiC, SiO2,silsesquioxanes, Cdoped oxides (i.e., organosilicates) that include atoms of Si, C, O andH, including porous versions of the foregoing, or combinations thereof.

Dielectric material 260 can be deposited utilizing any conventionaldeposition process including, but not limited to chemical vapordeposition (CVD), plasma enhanced chemical vapor deposition (PECVD),spin-on coating, evaporation, and chemical solution deposition. Spin-oncoating can be preferable by resulting in less overburden and therebyreducing the need for or demand upon a subsequent planarization stepsuch as CMP. Preferably, such coating can form a layer of uniform depthsuch that ILD etch back, rather than CMP, is sufficient to smooth thefirst-level surface and expose the top of the first-level via structuresprior to further formation of interconnect structure. Referring now toFIGS. 2E-1 and 2E-2, it may be advantageous to form dummy lines, e.g.216 and 217, which lines may not ultimately comprise the interconnectstructure but are formed simply to create a more uniform density ofstructures in a metal layer in order to promote ILD fill of such layerto a uniform depth.

Formation of the first metal layer is completed by a planarizationprocess if necessary, which could be, for example, chemical mechanicalpolishing and/or grinding to form the lower portion of the structureshown in FIG. 2F such that upper surface 266 is coplanar with exposedsurface 226. Typically, chemical mechanical polishing is employed.

Typically, the desired interconnect structure requires more than onemetal layer, and perhaps 10, 20, or even more metal layers.Conceptually, a second metal layer 420 can be deposited over the firstlayer, and patterned by OPL 442, optional hard mask 444, and photoresist445 in the same fashion as first metal layer 220. In any multi-levelintegration of interconnect wiring, it is important to form second levellines and vias such that they properly connect with underlying firstlevel lines and vias. In conventional dielectric damascene, metalinterconnect structure is formed within and after deposition of adielectric layer which is typically optically transparent, so alignmentcan be enabled by optically aligning upper masks and structures withunderlying structures. In subtractive metal etch it is not possible tosee metal features in the underlying layer by path 450, because thenewly deposited second metal layer is opaque.

This challenge can be overcome by embodiments of the present invention.FIG. 4A shows that prior to deposition of an opaque layer over a firstinterconnect layer 220, first dielectric 260 can be recessed by knownmethods such that portions of the first level via structures 221 and 222form topographic features that protrude by height r2 above the recessedsurface 276. The topographic features may be structures formedexclusively for the purpose of providing reference locations that map tounderlying features, or may be conductive features, that is, structuresthat actually constitute electrically active interconnect structure.Alternatively, prior to ILD fill as depicted by FIGS. 2E-1 or 2E-2, alayer such as an anti-nucleation layer that would inhibit ILD depositioncan be formed over upper portions of the topographic features.

According to such alternative embodiment, a planarizing ILD fill wouldleave such upper portions exposed such that ILD etch back prior todeposition of a second metal layer would be unnecessary. The ILDinhibiting layer could optionally be selectively removed, such as by wetetch, prior to deposition of the next metal layer.

Referring again to FIG. 4A, the distance r2 of this recess measured fromthe top surface 226 of structures 221 and 222 to the recessed surface276 may vary depending on the exact recess process and conditions usedand would be less than a via height (e.g., d2). Typically, and by way ofa non-limiting example, the distant of the recess is from about 2 toabout 100 nm, with a distant from about 10 to about 20 nm being evenmore typical. The dielectric recess process employed in the presentinvention in forming the structure shown in FIG. 4A includes any etchingprocess (including dry etching and chemical wet etching) thatselectively etches the dielectric material 260 relative to material ofstructures 221 and 222. Typically, the dielectric recess processemployed in the present invention includes a chemical etching process ora reactive ion etching process.

Now with reference to FIG. 4B, adhesion layer 410 can optionally beformed over recessed surface 276 as well as over exposed sidewalls andtop surfaces of the protruding structures. Layer 410 may alternativelyor additionally function as an etch stop layer or as an underlayer topromote desirable growth of material 420. Adhesion layer 410 can beformed by a deposition process including, for example, chemical vapordeposition (CVD), plasma enhanced chemical vapor deposition (PECVD),atomic layer deposition (ALD), physical vapor deposition (PVD),sputtering, chemical solution deposition and plating. The adhesion layer410 can comprise Ta, TaN, TaAlN, TiAlN, Ti, TiN, Ru, RuN, RuTa, RuTaN,W, WN or any other material that can enhance adhesion at the firstdielectric/second metal layer interface or can enhance thestructure/process in terms of etch stop or a growth promotion layer. Thethickness of the adhesion layer 410 may vary depending on the depositionprocess used as well as the material employed. Typically, the adhesionlayer 410 has a thickness from about 1 to about 10 nm, with a thicknessfrom about 2 to about 5 nm being more typical.

Opaque layer 420 can be formed over the recessed first layer, andpreferrably is formed by a non-planarizing technique such that opaquelayer depth d4 is substantially uniform throughout. By depositing orotherwise forming the opaque layer at a uniform depth directly on therecessed first layer (with or without optional adhesion layer 410), thetopography of the first layer can be duplicated and visible asprotrusions 481 and 482 of surface 426. Patterning of opaque layer 420can be aligned with underlying features by reference to protrusions 481and 482. Specifically, features 221 and 222 are respectively directlybelow protrusions 481 and 482, and the position of other first-layerfeatures such as 213 or the lines extending from vias 221 and 222 can bedirectly mapped to said protrusions.

Opaque layer 420 may comprise a conductive metal, including thematerials that can form first metal layer 220. The material of opaquelayer 420 can be the same or different from the material of first metallayer 220.

FIG. 4C shows layer 420 patterned according to the patterns of FIGS. 5Aand 5B by repeating the process of forming and patterning mask andphotoresist layers as described above for patterning layer 220. A maskcan be defined on layer 420 utilizing the pattern of FIG. 5A whichincludes mask elements 502 and 503, and element 501 which is merely areference location. The pattern of FIG. 5A could be positioned byaligning elements 501 and 502 directly over protrusions 481 and 482.Layer 420 can then be etched to depth d6. Layer 420 can then be etchedthrough the remaining depth d5 according to the pattern of FIG. 5B,where mask elements 504 and 505 are positioned by reference toprotrusions 424 and 426. If adhesion layer 410 is present, that partexposed by etching through layer 420 can be optionally removed byselective etch (not shown). Finally, the voids formed by etching layer420 can be filled by dielectric layer 460, which can be planarized suchthat the top of dielectric layer 460 is coplanar with exposed topsurface 426.

A third metal layer could be formed in the same manner as layer 420 byrecessing dielectric layer 460 to form a reference topography anddepositing such third metal layer so as to retain that referencetopography on its top surface.

FIG. 4C illustrates an embodiment wherein at least one protrusions ofthe underlying layer (222) becomes part of the vias in the overlyinglayer (428), but that need not be the case. For example, FIG. 6illustrates another embodiment where the mask is positioned and formedby reference to the protrusions, but does not actually cover theprotrusions. The structure resulting from such a mask could define linesand/or vias that do not connect to the protrusions of the underlyinglayer.

Referring again to FIG. 4C, via structure 428 in layer 420 has verticalor nearly vertical sides. FIG. 7 illustrates another embodiment whereinby modifying and controlling the metal etch process, structures withangled or shaped sides can be formed. The different tapered shapes canbe achieved by appropriate etch chemistries, for example by the using ofpolymerizing gases.

In yet another embodiment, the structure includes at least one layerformed by conventional dielectric damascene covered by at least onelayer formed by subtractive metal etch. Similar to the foregoingdescription regarding second metal layer 420, such embodiment would beformed by recessing the dielectric of such conventional damascene layerprior to depositing metal layer. The patterning of such metal layercould be accomplished just as described for layer 420.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

What is claimed is:
 1. An interconnect structure comprising: at leasttwo layers on a substrate, said layers comprising metal interconnectstructure embedded within dielectric material, each of said layershaving at least one via that extends to the top of said layer and atleast one line formed along the bottom of said layer, wherein said atleast one via of the lower of said layers extends into the upper of saidlayers.
 2. The interconnect structure of claim 1 wherein said at leastone via of said upper layer extends to said at least one via of thelower of said layers.
 3. The interconnect structure of claim 1 furthercomprising an adhesion layer formed between said at least two layers. 4.The interconnect structure of claim 1 wherein a surface of said at leastone line of said upper layer is in direct contact with an adhesionlayer, which adhesion layer is in direct contact with dielectricmaterial of said lower layer.
 5. An interconnect structure comprising:at least two dielectric layers on a substrate, said at least twodielectric layers each comprising a metal via and a metal line within asingle layer of dielectric material, wherein said metal line of eachsaid at least two dielectric layers is along the bottom of itsrespective dielectric layer.
 6. The interconnect structure of claim 5wherein said metal via of the upper of said at least two dielectriclayers consists essentially of tungsten.
 7. The interconnect structureof claim 5 wherein said metal line of the upper of said at least twodielectric layers consists essentially of tungsten.
 8. The interconnectstructure of claim 5 wherein said metal line of the upper of said atleast two dielectric layers intersects said metal via of the upper ofsaid at least two dielectric layers and said metal line of the upper ofsaid at least two dielectric layers consists essentially of tungstenexcept at the region of said intersection.
 9. The interconnect structureof claim 8 wherein said metal via of the upper of said at least twodielectric layers comprises a metal selected from the group consistingof Al, Ti, Ta, Cr, Mo, Ru, Rh, V, Hf, and alloys thereof.